This invention relates to data processors and busses.
Some modern processors use a parallel array of identical processors to perform tasks on incoming instructions and/or data. The parallel array can handle high instruction and/or data bandwidths if the various tasks are independent. Prior art routers have relied heavily on application specific integrated circuits (ASICs) to perform routing functions. Each ASIC is configured for a particular system. Different systems and/or communication protocols generally use different ASICs.
According to one aspect of the invention, a router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at each time. Each processor transfers control of the communications bus to another processor in response to receiving a request for control from the other processor.